1. Field of the Invention
The present invention relates to the field of current sources and, in particular, to a constant current source whose magnitude is proportional to capacitor ratios, reference voltage and switching frequency.
2. Background Art
Semiconductor circuits are comprised of a number of different elements, such as resistors, transistors, capacitors, etc. The operation of a semiconductor circuit often depends on the interaction of one or more of these elements. For proper interaction, the relative values of the interdependent elements must be within a desired range. Such a semiconductor circuit is known as a "process dependent" circuit. However, the nature of semiconductor circuit manufacturing is such that there is often variation in the actual values of circuit elements. If the actual values vary too greatly, the desired relative relationship between the elements may be such that the operation of the semiconductor circuit is compromised. This is referred to as "process mismatching".
It is desirable to construct semiconductor circuits whose operation is substantially independent from the values of any of its components. Such circuits are called "process invariant" circuits. A process invariant circuit is one whose operation is insulated from the unpredictable variations in component values and performance that may occur during normal manufacturing processes and operation.
One component often used in process invariant circuits is a current source. Prior art capacitor based current sources are discussed in detail below, along with their drawbacks. One application of prior art current sources is in a timer/delay circuit. The disadvantages of prior art current sources limit the performance of such timer/delay circuits. These performance limitations are described in detail below.
Prior art trim/compensation circuits are also discussed. To date, there are no adequate integral trim/compensation schemes for use in CMOS based circuits.
Many prior art current sources are resistor based. In other words, the output current is proportional to the value of one or more resistors in the current source. If the resistor based current source is used in a circuit that also is resistor based, then the non-linear effects of variations in the resistors' sizes and performance can often be "cancelled out" resulting in a process invariant circuit.
However, many different process invariant circuits are capacitor based, such as frequency tracking loop filters, charge pumps, process invariant PLL architecture and process invariant delay timers. Those circuits that are capacitor based (by design or through parasitic capacitance) cannot use a resistor based current source if process invariance is desired. To maintain process invariance, a capacitor based current source must be used.
In a typical capacitor based current source, the magnitude of the output current is proportional to (among other things) the values of the capacitors in the current source. A prior art capacitor based current source is presented in Kozaburo Kurita and Takashi Hotta, "PLL-Based BiCMOS On-Chip Clock Generator for Very High Speed Microprocessor," Journal of Solid State Circuits 26.4 (April 1991): 586.
A block diagram of this prior art capacitor based current source is illustrated in FIG. 4(A). This current source uses pulse width modulation and low pass filtering to generate output current I.sub.1. Frequency divider 401 receives input signal F.sub.in and produces a single output V.sub.0. Output V.sub.0 is an oscillating signal, and is fed into integrator 402. Integrator 402 integrates output V.sub.0, producing ramp signal V.sub.1 and providing V.sub.1 to comparator 403. Comparator 403 compares ramp signal V.sub.1 to reference 404, providing a pulse width modulated (PWM) signal V.sub.2 to charge pump 405. Charge pump 405 charges and discharges an internal capacitor at a rate governed by the PWM signal V.sub.2, producing voltage V.sub.3. Voltage V.sub.3 approximates a DC signal, but contains some unwanted AC components, so it is fed into filter 406. Filter 406 removes some of the AC components from signal V.sub.3 and provides output current I.sub.1. This output current is also provided to integrator 402 via feedback loop 407.
A circuit diagram of this prior art capacitor based current source is illustrated in FIG. 1(A). Clock input F.sub.in is coupled to frequency divider 401. Frequency divider 401 divides the frequency of clock input F.sub.in by two to generate a 50% duty cycle clock output at node 101. This 50% duty cycle clock signal is provided to integrator 402 at node 101. The voltage at node 101 is V.sub.0.
Integrator 402 is now described. Integrator 402 consists generally of transistors 103-104 and capacitor C.sub.1. Node 101 is coupled to the gates of PMOS transistor 103 and NMOS transistor 104. The source of transistor 104 is coupled to voltage source VNA. The drain of transistor 104 is coupled to node 106. The drain of transistor 103 is also coupled to node 106, and the source of transistor 103 is coupled to the drain of transistor 105. The source of transistor 105 is coupled to voltage source VPA. One terminal of capacitor C.sub.1 is coupled to voltage source VNA, and the other terminal is coupled to node 106. The voltage at node 106 is V.sub.1.
Voltage V.sub.1 is connected to the inverting input of comparator 403. The non-inverting input of comparator 403 is coupled to reference voltage V.sub.b. The output of comparator 403 is fed into charge pump 405 at node 120. The voltage at node 120 is V.sub.2.
Charge pump 405 is now described. Charge pump 405 is generally comprised of transistors 110 and 111, current sources I.sub.3 and I.sub.4, and capacitor 112. Node 120 is coupled to the gates of PMOS transistor 110 and NMOS transistor 111. The source of transistor 111 is coupled to voltage source VNA through current source I.sub.4. The drain of transistor 111 is coupled to the drain of transistor 110 at node 125. The source of transistor 110 is coupled to voltage source VPA through current source I.sub.3. The voltage at node 125 is V.sub.3. The first terminal of capacitor 112 is coupled to node 125 and the second terminal is coupled to voltage source VNA. The output of charge pump 405 is fed into low pass filter 406 at node 125. The voltage at node 130 is V.sub.4.
Low pass filter 406 consists of resistor 113 and capacitor 114. The first terminal of resistor 113 is coupled to node 125, and the second terminal of resistor 113 is coupled to voltage source VNA through capacitor 114, and to the gates of PMOS transistors 105 and 115. The source of transistor 115 is coupled to voltage source VPA. Output current I.sub.1 of the prior art current source is taken from the drain of transistor 115. Transistors 105 and 115 form a current mirror so that the current I.sub.1 ' flowing through transistor 105 is equal to output current I.sub.1 flowing through transistor 115.
The waveforms of the current source of FIG. 1(A) are illustrated in FIG. 1(B). During the first half period of the 50% duty cycle clock signal, voltage V.sub.0 is low, so NMOS transistor 104 is non-conducting ("turned-off") and PMOS transistor 103 is conducting ("turned-on"). Capacitor C.sub.1 is charged by current I.sub.1 ', which originates at the drain of transistor 105 and is equal to output current I.sub.1. Current I.sub.1 ' charges up capacitor C.sub.1, causing voltage V.sub.1 to ramp up. Comparator 403 compares capacitor voltage V.sub.1 to reference bias voltage V.sub.b and outputs a pulse width modulated (PWM) signal at node 120 (voltage V.sub.2) when voltage V.sub.1 exceeds reference voltage V.sub.b. The PWM signal drives charge pump 405. The charge pump circuit is controlled by voltage V.sub.2 at node 120, and charges capacitor 112 by the "pump-up" current I.sub.3 while the PWM signal is generated. The output voltage V.sub.3 of charge pump 405 is smoothed by low pass filter 406, comprised of resistor 113 and capacitor 114, to produce output voltage V.sub.4.
Output voltage V.sub.4 of low pass filter 406 controls output current I.sub.1 of transistor 115. Voltage V.sub.4 also controls the charging current of integrator 402 by controlling the gate voltage of PMOS transistor 105. During the second half period of the 50% duty cycle clock signal, voltage V.sub.0 is high, so transistor 103 is turned off and transistor 104 is turned on. This allows capacitor C.sub.1 to discharge rapidly. Voltage V.sub.1 drops below reference voltage V.sub.b and V.sub.2 at the output of comparator 403 goes from low to high. Transistor 110 turns off and transistor 111 turns on, discharging capacitor 112 by the "pump-down" current I.sub.4 and resetting the circuit for the start of the next clock period.
The steady state condition at node 125 is defined by:
Charge accumulated in capacitor 112=charge discharged by capacitor 112 EQU (t.sub.0 -t.sub.1)*I.sub.3 =(t.sub.0 +t.sub.1)*I.sub.4 EQU (t.sub.0 *I.sub.3)-(t.sub.1 *I.sub.3)=(t.sub.0 *I.sub.4)+(t.sub.1 *I.sub.4) EQU t.sub.1 *(I.sub.3 +I.sub.4)=t.sub.0 *(I.sub.3 -I.sub.4) EQU t.sub.1 =t.sub.0 *(I.sub.3 -I.sub.4)/(I.sub.3 +I.sub.4)
where EQU t.sub.0 =1/F.sub.in
From FIGS. 1(A) and 1(B), it follows that the charge Q.sub.1 present at node V.sub.1 at the end of time period t.sub.1 is EQU Q.sub.1 =t.sub.1 *I.sub.1 =V.sub.b *C.sub.1
so that output current I.sub.1 of the prior art current source is given by ##EQU1##
Output current I.sub.1 of the prior art capacitor base current source is proportional to the bias voltage V.sub.b, the value of capacitor C.sub.1, and the input frequency F.sub.in.
There are several disadvantages associated with the prior art current source. First, as in many PWM schemes, generating a PWM pulse requires comparator 403 to be a high speed comparator (on the order of 200 MHz). Comparator 403 must have equal rise and fall times, and equal delay and storage times. The rise/fall and delay/storage times of comparator 403 influence the effective t.sub.0 and t.sub.1 of the current source. If comparator 403 is not high speed, t.sub.0 and t.sub.1 will be skewed, and the PWM scheme will be non-linear. That is, output current I.sub.1 of the current source will be a non-linear function of the input frequency F.sub.in.
Second, the prior art current source requires short response times for current sources I.sub.3 and I.sub.4. Fast response times very small transients during turn-on and turn-off of I.sub.3 and I.sub.4 are required to prevent additional non-linearity in the transfer function of the prior art current source.
To facilitate circuit design, the output of a current source should be a linear function of the input signal. The main disadvantage of the prior art approach is the need for several high-speed high-performance components to maintain linearity in the transfer function. High speed devices may be possible in bipolar or BiCMOS circuits, but are not practical in a CMOS only technology.
Because of the high speed switching requirements of the prior art capacitor based current source, only resistor based current sources are available for use in a CMOS only technology. There exists a need for a CMOS frequency and capacitor based current source that can be used in process invariant capacitor based CMOS circuits. For example, such a frequency and capacitor based current source could be used in a basic timer or delay circuit. FIG. 8(A) illustrates a capacitor based timer or delay circuit of the prior art. Input V.sub.in of the circuit is coupled to the gates of PMOS transistor 803 and NMOS transistor 804. The source of transistor 803 is coupled to the first terminal of capacitor C.sub.t and to the positive terminal of voltage source V.sub.trip. The drain of transistor 803 is coupled to the drain of transistor 804, the second terminal of capacitor C.sub.t, and the inverting input of comparator 807. The negative terminal of voltage source V.sub.trip is coupled to the non-inverting input of the comparator 807. The source of transistor 804 is coupled to a resistor based constant current source 801. The current I of current source 801 is equal to V.sub.r /R, where V.sub.r is an internal reference voltage and R is the effective resistance of current source 801. Reset input RST is coupled to comparator 807, and is used to reset the comparator once the delayed pulse has been generated.
The waveforms of the timer/delay circuit are shown in FIG. 8(B). Input V.sub.in is a voltage pulse. Transistors 803 and 804, and capacitor C.sub.t, act as a ramp generator, charging and discharging capacitor C.sub.t at a fixed rate. Comparator 807 is used to determined when the voltage V.sub.cap on capacitor C.sub.t exceeds a threshold value (V.sub.trip).
The total delay T.sub.del introduced by the timer/delay circuit of FIG. 8(A) is given by EQU T.sub.del =V.sub.trip *C.sub.t /I+T.sub.comp
where I=V.sub.r /R is the magnitude of the current source, and T.sub.comp is the intrinsic delay of comparator 807. Substituting for I, the total delay T.sub.del is then EQU T.sub.del =(V.sub.trip /V.sub.r)*C.sub.t *R+T.sub.comp
The effects of the voltages V.sub.trip and V.sub.r on the total delay T.sub.del can be cancelled out if V.sub.r is a function of V.sub.trip or visa versa. However, variations in the values or performance of resistor R and capacitor C.sub.t cannot be cancelled out because there is no relationship between the two component values. To compensate against the effects of resistor and capacitor value and performance variations, the current I is generally trimmed in such a way as to trim the effect of capacitor C.sub.t. This trimming process requires the circuit designer to first measure the untrimmed total delay T.sub.del of the timer/delay circuit to determine the required trim value. This is a time consuming and tedious process.
FIG. 3(A) illustrates a typical prior art trim/compensation scheme as applied to a current mirror. The current mirror consists of PMOS transistors 301 and 302. The sources of transistors 301 and 302 are connected to voltage supply VPA. The gates of transistors 301 and 302 are connected to the drain of transistor 301 which has drain current I flowing through it. The drain of transistor 302 is connected to circuit 305.
All of the other components in FIG. 3(A) relate to the prior art trim/compensation scheme. The gates of PMOS transistors 303 and 304 are connected to the gate of transistor 301. The sources of transistors 303 and 304 are connected to voltage source VPA. The drain of transistor 303 is connected to the source of PMOS transistor 308. The drain of transistor 308 is connected to circuit 305. The gate of transistor 308 is connected to the first terminal of resistor 310 and the second terminal of zener diode 312. The second terminal of resistor 310 is connected to voltage supply VPA, and the first terminal of zener diode 312 is connected to ground. The drain of transistor 304 is connected to the source of PMOS transistor 309. The drain of transistor 309 is connected to circuit 305. The gate of transistor 309 is connected to the first terminal of resistor 311 and the second terminal of zener diode 313. The second terminal of resistor 311 is connected to voltage supply VPA, and the first terminal of zener diode 313 is connected to ground.
Zener diodes 312 and 313 do not allow current to flow through resistors 310 and 311 to ground. Consequently, nodes 315 and 316 are held at voltage VPA, transistors 308 and 309 are turned off, and no current is flowing through transistors 303 and 304 (I.sub.1 =I.sub.2 =0).
The circuit in FIG. 3(A) is designed to trim the input current I.sub.in so that it is equal to the drain current I flowing through transistor 301. To see how this works, suppose that after manufacturing the current mirror, current I.sub.0 supplied by transistor 302 is only equal to 0.90I. Assume also that transistor 303 is 5% of the physical size of transistors 301 and 302, and that transistor 304 is 1%. The value of current I.sub.in should be as close to that of current I as possible. To achieve this, a very large input signal is applied at Input.sub.2 to "zap," or break down, zener diode 312. After zener diode 312 is "zapped," we remove the signal at Input.sub.2 so that resistor 310 is shorted to ground. Grounding node 315 lowers the gate voltage of transistor 308 and allows current I.sub.1 to flow into circuit 305. Current I.sub.in is now equal to I.sub.0 +I.sub.1 =0.90I+0.05I=0.95I.
By "turning on" additional trimming transistors (such as 304), current I.sub.in can be increased until it is as close as possible to current I. Generally, the "zener zap" trimming process involves five steps:
1. Apply power and signal to circuit to be compensated.
2. Measure the resultant output (current, voltage or frequency).
3. Adjust the trim until the resultant output is within the desired specification.
4. "Burn-in" the trim value by "zapping" the anti-fuse (or fuse). Typically, the anti-fuse is a zener diode.
5. Repeat step 2 and check to see if the new resultant output remained within specification. If not, then fail the part.
The "zener zapping" method of compensation is time-consuming and inaccurate. The measuring/zapping procedure itself may take 5-10 seconds per compensation to accomplish. Further, often the "fuse" resists zapping, or is already zapped as a result of production. Also, zener zapping is permanent, i.e., once a circuit has been "zapped" compensation cannot be reversed. Thus, component performance "drifting" due to time and temperature variations cannot be compensated for with the zener zapping method.
Another prior art technique for trimming is illustrated in FIG. 3(B). The zener diode configuration of FIG. 3(A) is replaced with priority encoder 306. Priority encoder 306 is connected to nodes 315 and 316 through lines 317 and 318. Input 330 enables priority encoder 306 to monitor the input current I.sub.in to circuit 305. Outputs E.sub.1 and E.sub.2 are connected to nodes 315 and 316 of FIG. 3(A). By monitoring current I.sub.in priority encoder 306 determines which trimming components should be activated to best match current I.sub.in to current I. For example, instead of "zapping" zener diode 312 to turn on transistor 308 as described above, priority encoder 306 simply changes output E1 from high to low.
The use of priority encoders in trim/compensation schemes is an improvement over the "zener zapping" trimming process. The priority encoder is quicker, more reliable and able to adjust compensation levels "on the fly" by switching trimming components in or out as needed to compensate for drift due to time or temperature variations.
One factor that is often trimmed or compensated for is the RC time constant of a circuit. Unfortunately, using the priority encoder in conjunction with additional circuitry, circuit designers are able to trim the values of R and C separately, but are unable to trim the product of RC simultaneously. This results in inefficient and often inaccurate trimming.